{"id":36910,"date":"2024-07-18T02:52:03","date_gmt":"2024-07-18T02:52:03","guid":{"rendered":"https:\/\/essays.homeworkacetutors.com\/2024\/07\/definitions-of-relevant-terminology-information-technology-essay\/"},"modified":"2024-07-18T02:52:03","modified_gmt":"2024-07-18T02:52:03","slug":"definitions-of-relevant-terminology-information-technology-essay","status":"publish","type":"post","link":"https:\/\/www.colapapers.com\/us\/definitions-of-relevant-terminology-information-technology-essay\/","title":{"rendered":"Definitions Of Relevant Terminology Information Technology Essay"},"content":{"rendered":"
\n

Field-Programmable Device (FPD)- a general term that refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured \u201cin-system\u201d. Another name for FPDs is programmable logic devices (PLDs); although PLDs encompass the same types of chips as FPDs, we prefer the term FPD because historically the word PLD has referred to relatively simple types of devices.<\/p>\n

\u00e2\u20ac\u00a2 PLA \u2013 a Programmable Logic Array (PLA) is a relatively small FPD that contains two levels of logic, an AND-plane and an OR-plane, where both levels are programmable (note: although PLA structures are sometimes embedded into full-custom chips, we refer here only to those PLAs that are provided as separate integrated circuits and are user-programmable).<\/p>\n

\u00e2\u20ac\u00a2 PAL- a Programmable Array Logic (PAL) is a relatively small FPD that has a programmable AND-plane followed by a fixed OR-plane<\/p>\n

\u00e2\u20ac\u00a2 SPLD \u2013 refers to any type of Simple PLD, usually either a PLA or PAL<\/p>\n

\u00e2\u20ac\u00a2 CPLD \u2013 a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip. Alternative names (that will not be used in this paper) sometimes adopted for this style of chip are Enhanced PLD (EPLD), Super PAL, Mega PAL, and others.<\/p>\n

\u00e2\u20ac\u00a2 FPGA \u2013 a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity. Whereas CPLDs feature logic resources with a wide number of inputs (AND planes), FPGAs offer more narrow logic resources. FPGAs also offer a higher ratio of flip-flops to logic resources than do CPLDs.<\/p>\n

\u00e2\u20ac\u00a2 HCPLDs \u2013 high-capacity PLDs: a single acronym that refers to both CPLDs and FPGAs. This term has been coined in trade literature for providing an easy way to refer to both types of devices.<\/p>\n

\u00e2\u20ac\u00a2 Interconnect -the wiring resources in an FPD.<\/p>\n

\u00e2\u20ac\u00a2 Programmable Switch \u2013 a user-programmable switch that can connect a logic element to an interconnect wire, or one interconnect wire to another<\/p>\n

\u00e2\u20ac\u00a2 Logic Block \u2013 a relatively small circuit block that is replicated in an array in an FPD. When a circuit is implemented in an FPD, it is first decomposed into smaller sub-circuits that can each be mapped into a logic block. The term logic block is mostly used in the context of FPGAs, but it could also refer to a block of circuitry in a CPLD.<\/p>\n

\u00e2\u20ac\u00a2 Logic Capacity- the amount of digital logic that can be mapped into a single FPD. This is<\/p>\n

usually measured in units of \u201cequivalent number of gates in a traditional gate array\u201d. In other<\/p>\n

words, the capacity of an FPD is measured by the size of gate array that it is comparable to. In simpler terms, logic capacity can be thought of as \u201cnumber of 2-input NAND gates\u201d.<\/p>\n

\u00e2\u20ac\u00a2 Logic Density- the amount of logic per unit area in an FPD.<\/p>\n

\u00e2\u20ac\u00a2 Speed-Performance \u2013 measures the maximum operable speed of a circuit when implemented in an FPD. For combinational circuits, it is set by the longest delay through any path, and for sequential circuits it is the maximum clock frequency for which the circuit functions properly.<\/p>\n

PROGRAMMABLE LOGIC DEVICES<\/h2>\n

A programmable logic device or PLD is an electronic component used to build digital circuits. Unlike a logic gate, which has a fixed function, a PLD has an undefined function at the time of manufacture. Before the PLD can be used in a circuit, it must be programmed. These were the first chips that could be used to implement a flexible digital logic design in hardware. Other names we might encounter for this class of device are Programmable Logic Array (PLA), Programmable Array Logic (PAL), and Generic Array Logic (GAL).<\/p>\n

Programmable logic devices (PLDs) are divided into 3 basic architecture types, SPLD, CPLD and FPGA. Figure 3.1 shows the architecture tree of PLD.<\/p>\n

Fig 3.1 PLD Architecture Tree<\/p>\n

PLD Applications<\/h2>\n

\u00e2\u20ac\u00a2 Glue Logic<\/p>\n

\u00e2\u20ac\u00a2 State Machines<\/p>\n

\u00e2\u20ac\u00a2 Synchronization<\/p>\n

\u00e2\u20ac\u00a2 Decoders<\/p>\n

\u00e2\u20ac\u00a2 Counters<\/p>\n

\u00e2\u20ac\u00a2 Bus Interfaces<\/p>\n

\u00e2\u20ac\u00a2 Parallel-to-Serial<\/p>\n

\u00e2\u20ac\u00a2 Serial-to-Parallel<\/p>\n

\u00e2\u20ac\u00a2 Subsystems<\/p>\n

\u00e2\u20ac\u00a2 and Many Others<\/p>\n

Why PLDs?<\/h2>\n

\u00e2\u20ac\u00a2 Increased Integration. You can reduce the package count of your designs while simultaneously increasing the features offered by your product.<\/p>\n

\u00e2\u20ac\u00a2 Lower Power. CMOS and fewer packages combine to reduce power consumption.<\/p>\n

\u00e2\u20ac\u00a2 Improved Reliability. Lower power plus fewer interconnections and packages translate into greatly improved system reliability.<\/p>\n

\u00e2\u20ac\u00a2 Lower Cost. PLDs reduce inventory costs, too.<\/p>\n

\u00e2\u20ac\u00a2 Easier To Use! Yes, believe it or not, once you get past the initial learning period, PLDs are easier to use than discrete logic functions.<\/p>\n

\u00e2\u20ac\u00a2 Easier to Change. Oops! Need to make a change? You won\u2019t need \u201cblue wire\u201d when you use a PLD \u2013 all changes are internal,and can be done quickly. ECNs are a snap \u2013 and system reliability is maintained!<\/p>\n

FPGA Field Programmable Gate Array<\/h2>\n

Field-programmable gate array is an emerging technology around the worldwide. FPGA market will be double the value and expected to grow more than $3 billion by 2010.FPGA technology is and its invention by Xilinx in 1984, FPGAs have gone from being simple glue logic chips to actually replacing custom application-specific integrated circuits (ASICs) and processors for signal processing and control applications<\/p>\n

FPGA?<\/h2>\n

FPGA chip adoption across all industries is driven by the fact that FPGAs combine the best parts of ASICs and processor-based systems. FPGAs provide hardware-timed speed and reliability, but they do not require high volumes to justify the large upfront expense of custom ASIC design. Reprogrammable silicon also has the same flexibility of software running on a processor-based system, but it is not limited by the number of processing cores available. Unlike processors, FPGAs are truly parallel in nature so different processing operations do not have to compete for the same resources. Each independent processing task is assigned to a dedicated section of the chip, and can function autonomously without any influence from other logic blocks. As a result, the performance of one part of the application is not affected when additional processing is added.<\/p>\n

FPGA: Field Programmable Gate Array. Conceptually it can be considered as an array of Configurable Logic Blocks (CLBs) that can be connected together through a vast interconnection matrix to form complex digital circuits.<\/p>\n

Figure 2. Exploded view of a typical FPGA<\/p>\n

FPGAs have traditionally found use in highspeed custom digital applications where designs tend to be more constrained by performance rather than cost. The explosion of integration and reduction in price has led to the more recent widespread use of FPGAs in common embedded applications.<\/p>\n

FPGAs, along with their non-volatile cousins CPLDs (Complex Programmable Logic Devices), are emerging as the next digital revolution that will bring about change in much the same way that microprocessors did. With current highend devices exceeding 2000 pins and topping billions of transistors, the complexity of these devices is such that it would be impossible to program them without the assistance of highlevel design tools. Xilinx, Altera, Actel, and Lattice all offer highend EDA tool suites designed specifically to support their own devices however they also offer free versions aimed at supporting the bulk of FPGA development. These vendors understand the importance of tool availability to increased silicon sales and they all seem committed to supporting a free version of their tools for the foreseeable future. Through the use of EDA tools, developers can design their custom digital circuits using either schematic based techniques, VHDL, Verilog or any combination of these methods.<\/p>\n

VLSI DESIGN<\/h2>\n

VLSI Design can be classified based on the Prototype,<\/p>\n

ASIC<\/p>\n

FPGA<\/p>\n

ASIC- Application Specific Integrated Circuits.<\/h2>\n

An application-specific integrated circuit (ASIC) is an integrated circuit (IC) customized for a particular use, rather than intended for general-purpose use. For example, a chip designed solely to run a cell phone is an ASIC. Intermediate between ASICs and industry standard integrated circuits, like the 7400 or the 4000 series, are application specific standard products.<\/p>\n

Figure 31. ASIC DESIGN FLOW<\/h2>\n

Implementing Process in FPGA or CPLD<\/h2>\n

Implementing FPGA or CPLD logic needs development software usually consists of the following steps:<\/p>\n

Write a program for the logic circuit using a hardware description language (HDL) either VHDL or Verilog.<\/p>\n

Using Logic synthesis tool check the syntax and convert the code into gate level netlist. The netlist is just a description of the various logic gates in the design and how they are interconnected.<\/p>\n

Using the implementation tools like Xilinx ISE or Altera Quartus II to map the logic gates and interconnections into the FPGA. The mapping tool collects netlist gates into groups that fit into the LUTs and then the place & route tool assigns the gate collections to specific CLBs while opening or closing the switches in the routing matrices to connect the gates together.<\/p>\n

After this, a program extracts the state of the switches in the routing matrices and generates a bit stream where the ones and zeroes correspond to open or closed switches.<\/p>\n

The bit stream is downloaded into a physical FPGA chip.\u00a0 The electronic switches in the FPGA open or close in response to the binary bits in the bit stream.\u00a0 Upon completion of the downloading, the FPGA will perform the operations specified by HDL code or schematic.\u00a0 Apply input signals to the I\/O pins of the FPGA to check the operation of design.<\/p>\n

Fig 3.7 The CPLD or FPGA Design Flow<\/p>\n<\/div>\n","protected":false},"excerpt":{"rendered":"

Field-Programmable Device (FPD)- a general term that refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured […]<\/p>\n","protected":false},"author":5,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[7348,5863,7336],"tags":[7341,7337,7340,7338,7339],"class_list":["post-36910","post","type-post","status-publish","format-standard","hentry","category-ace-homework-tutors-information-technology","category-information-technology","category-write-my-essay-for-me-2","tag-affordable-essay-pro-papers-uk","tag-assist-with-thesis-writing-online","tag-complimentary-essay-example","tag-online-dissertation-help-from-phd-experts","tag-top-u-s-dissertation-writing-services"],"_links":{"self":[{"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/posts\/36910","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/users\/5"}],"replies":[{"embeddable":true,"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/comments?post=36910"}],"version-history":[{"count":0,"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/posts\/36910\/revisions"}],"wp:attachment":[{"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/media?parent=36910"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/categories?post=36910"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/www.colapapers.com\/us\/wp-json\/wp\/v2\/tags?post=36910"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}